Die letzten Meldungen

SYSTEMAUSBILDUNG im SoSe 2017 „Grundlagen und Aspekte von Betriebssystemen und systemnahen Diensten”

21. April 2017

Mit Beginn des Sommersemesters 2017 setzt das RRZE auch seine Veranstaltungsreihe „SYSTEMAUSBILDUNG – Grundlagen und Aspekte von Betriebssystemen und systemnahen Diensten“ fort und lädt Sie herzlich zu seinen Vorträgen ein.
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Wartungsankündigung für „campo“ am 27.04.2017

19. April 2017

Aufgrund von Wartungsarbeiten wird das campo-Portal am Donnerstag, 27. April 2017 zwischen 15:00 Uhr und 19:00 Uhr nicht zur Verfügung stehen.
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Wartung der FAUbox

18. April 2017

Am Mittwoch, 19.04.2017 wird die FAUbox ein Versionsupgrade erhalten. Wir nutzen das Wartungsfenster des Loadbalancers. Start der Arbeiten wird 15:00 Uhr sein. Ende der Arbeiten an der FAUbox wird voraussichtlich um 15:30 sein.
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Meldungen nach Thema

 

Optimizations for stencil algorithms on multi-core systems

General Remarks

This project develops optimization techniques for stencil-based algorithms like the Jacobi and Gauss-Seidel smoothers and the lattice-Boltzmann method (LBM). While much work has been done in the past in this field, the current trend towards multi-core chips with complex cache topologies requires a re-evaluation of existing approaches and the development of new ideas that put the specific features of those processors to use.

Potentials of temporal blocking for stencil-based computations on multi-core systems

Master's thesis at the Externer Link:  Georg Simon Ohm University of Applied Sciences Nuremberg.

Author: Markus Wittmann (now RRZE)

Supervisor: Georg Hager (HPC Services).

Abstract:The "DRAM Gap", i.e. the discrepancy between theoretical peak performance and memory bandwidth of a processor chip, has been worsening over the last two decades. This trend is currently even accelerating due to the advent of multi- and many-core processors. Therefore, new algorithms and optimization techniques must be developed in order to diminish the applications' hunger for memory bandwidth. Stencil codes, which are frequently used at the core of fluid flow simulations (like lattice-Boltzmann solvers) and PDE solvers including multi-grid methods, can break new performance grounds by improving temporal locality. This thesis is concerned with several different variants of temporal blocking, with a special emphasis on leveraging shared caches in multi-core environments. The developed optimization methods are thoroughly benchmarked and analyzed on three different processor architectures. Finally it is shown how temporal blocking, whose applicability is traditionally limited to shared-memory systems, can be employed on distributed-memory parallel computers.

Downloads: PDF: Poster (on display at Externer Link:  SC09, Portland, OR), PDF: Thesis.

Publications

G. Wellein, G. Hager, T. Zeiser, M. Wittmann and H. Fehske: Efficient temporal blocking for stencil computations by multicore-aware wavefront parallelization. Proc. COMPSAC 2009. Best Paper Award! DOI:Externer Link:  10.1109/COMPSAC.2009.82

M. Wittmann, G. Hager and G. Wellein: Multicore-aware parallel temporal blocking of stencil codes for shared and distributed memory. Accepted for Workshop on Large-Scale Parallel Processing (LSPP) 2010, April 23rd, Atlanta, GA. Externer Link:  arXiv:0912.4506

Contact

Project manager:

  • Prof. Dr. Gerhard Wellein
    Erlangen Regional Computing Center
    HPC Services
    Martensstr. 1
    91058 Erlangen
    +49 (0)9131 85 28136
    gerhard.wellein@rrze.fau.de

Letzte Änderung: 13. Maerz 2012, Historie

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