Sprungmarken

Die letzten Meldungen

RRZE-Betrieb am „Berch“-Dienstag

20. Mai 2015

Am Dienstag, den 26.05.2015, wird das RRZE ab 12 Uhr geschlossen.
Weiterlesen...

Zusätzliche Kurstermine am IT-Schulungszentrum

19. Mai 2015

Da einige Kurse in unserem aktuellen Programm bereits ausgebucht sind, haben wir für Ende Juli und Anfang August zusätzliche Veranstaltungen eingeplant.
Weiterlesen...

Ankündigung einer Netzwartung

13. Mai 2015

Wartungsdatum: 18.05.2015
Weiterlesen...

Meldungen nach Thema

 

Optimizations for stencil algorithms on multi-core systems

General Remarks

This project develops optimization techniques for stencil-based algorithms like the Jacobi and Gauss-Seidel smoothers and the lattice-Boltzmann method (LBM). While much work has been done in the past in this field, the current trend towards multi-core chips with complex cache topologies requires a re-evaluation of existing approaches and the development of new ideas that put the specific features of those processors to use.

Potentials of temporal blocking for stencil-based computations on multi-core systems

Master's thesis at the Externer Link:  Georg Simon Ohm University of Applied Sciences Nuremberg.

Author: Markus Wittmann (now RRZE)

Supervisor: Georg Hager (HPC Services).

Abstract:The "DRAM Gap", i.e. the discrepancy between theoretical peak performance and memory bandwidth of a processor chip, has been worsening over the last two decades. This trend is currently even accelerating due to the advent of multi- and many-core processors. Therefore, new algorithms and optimization techniques must be developed in order to diminish the applications' hunger for memory bandwidth. Stencil codes, which are frequently used at the core of fluid flow simulations (like lattice-Boltzmann solvers) and PDE solvers including multi-grid methods, can break new performance grounds by improving temporal locality. This thesis is concerned with several different variants of temporal blocking, with a special emphasis on leveraging shared caches in multi-core environments. The developed optimization methods are thoroughly benchmarked and analyzed on three different processor architectures. Finally it is shown how temporal blocking, whose applicability is traditionally limited to shared-memory systems, can be employed on distributed-memory parallel computers.

Downloads: PDF: Poster (on display at Externer Link:  SC09, Portland, OR), PDF: Thesis.

Publications

G. Wellein, G. Hager, T. Zeiser, M. Wittmann and H. Fehske: Efficient temporal blocking for stencil computations by multicore-aware wavefront parallelization. Proc. COMPSAC 2009. Best Paper Award! DOI:Externer Link:  10.1109/COMPSAC.2009.82

M. Wittmann, G. Hager and G. Wellein: Multicore-aware parallel temporal blocking of stencil codes for shared and distributed memory. Accepted for Workshop on Large-Scale Parallel Processing (LSPP) 2010, April 23rd, Atlanta, GA. Externer Link:  arXiv:0912.4506

Contact

Project manager:

  • Prof. Dr. Gerhard Wellein
    Erlangen Regional Computing Center
    HPC Services
    Martensstr. 1
    91058 Erlangen
    +49 (0)9131 85 28136
    gerhard.wellein@rrze.fau.de

Letzte Änderung: 13. Maerz 2012, Historie

zum Seitenanfang

Startseite | Kontakt | Impressum

RRZE - Regionales RechenZentrum Erlangen, Martensstraße 1, D-91058 Erlangen | Tel.: +49 9131 8527031 | Fax: +49 9131 302941

Inhaltenavigation

Zielgruppennavigation

  1. Studierende
  2. Beschäftigte
  3. Einrichtungen
  4. IT-Beauftragte
  5. Presse & Öffentlichkeit