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24. März 2015

Ankündigung einer Wartung der zentralen USV-Anlage (Unterbrechungsfreie StromVersorgung) des Rechenzentrums.
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Ankündigung einer Stromabschaltung am 27.03.2015 von 8.30 Uhr bis 9.30 Uhr

23. März 2015

Ankündigung einer Stromabschaltung am Freitag, 27.03.2015 von 8.30 bis 9.30 Uhr.
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17. März 2015

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Mitarbeiter

Dr. Georg Hager

Abteilung Zentrale Systeme

Anschrift

Martensstraße 1
91058 Erlangen

Publikationen

2014

2012

2011

2010

2009

  • Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    Benchmark analysis and application results for lattice Boltzmann simulations on NEC SX vector and Intel Nehalem systems
    In: Parallel Processing Letters 19 (2009), S. 491-511
    [DOI: 10.1142/S0129626409000389]
    [URL: http://www.worldscinet.com/ppl/19/1904/S0129626409000389.html]

  • Wellein, Gerhard; Hager, Georg; Zeiser, Thomas; Wittmann, Markus; Fehske, Holger;
    Efficient temporal blocking for stencil computations by multicore-aware wavefront parallelization
    In: -; (Hrsg:) Proceedings of 2009 33rd Annual IEEE International Computer Software and Applications Conference
    (COMPSAC 2009, Seattle, USA, Juli 20 -24, 2009)
    IEEE Computer Society : IPSJ/IEEE SAINT Conference, DOI 10.1109/COMPSAC.2009.82, 2009, S. 579-586.

  • Wellein, Gerhard; Hager, Georg; Zeiser, Thomas; Wittmann, Markus; Fehske, Holger;
    Efficient temporal blocking for stencil computations by multicore-aware wavefront parallelization
    Vortrag: 33rd Annual IEEE International Computer Software and Applications Conference (COMPSAC 2009), Best Paper Award
    Seattle (WA, USA), 20-24.Juli.2009

  • Wellein, Gerhard; Hager, Georg; Zeiser, Thomas; Fehske, Holger; Wittmann, Markus; Habich, Johannes; Treibig, Jan;
    Enabling temporal blocking for stencil computations by multicore-aware wavefront parallelization
    Vortrag: CSE Seminar, UC Berkeley and Lawrence Berkeley National Laboratory
    Berkeley, CA, USA, 15.Mai.2009

  • Habich, Johannes; Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    Enabling temporal blocking for a lattice Boltzmann flow solver through multicore aware wavefront parallelization
    Vortrag: ParCFD 2009 Conference, NASA AMES
    Moffet Field (CA, USA), 19.Mai.2009

  • Rabenseifner, Rolf; Hager, Georg; Jost, Gabriele;
    Hybrid MPI/OpenMP Parallel Programming on Clusters of Multi-Core SMP Nodes
    In: -; (Hrsg:) Proceedings of PDP 2009
    (17th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, Weimar, 18-20 February 2009)
    Weimar : Bauhaus-University Weimar, 2009, S. 1-10.

  • Jost, G.; Koniges, A.; Wellein, Gerhard; Hager, Georg; Rabenseifner, R. ;
    Hybrid OpenMP/MPI Programming and Other Models for Multi-Core Architectures
    Vortrag: ParCFD 2009 Conference, NSAS AMES
    Moffet Field (CA, USA), 18.Mai.2009

  • Habich, Johannes; Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    Multicore-aware wavefront parallelization of a lattice Boltzmann flow solver
    Vortrag: 6th International Conference for Mesosocopic Methods in Engineering and Science (ICMMES)
    Guangzhou, China, Juli.2009

  • Habich, Johannes; Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    Performance Evaluation of Numerical Compute Kernels on GPUs
    Vortrag: First International Workshop on Computational Engineering - Special Topic Fluid-Structure Interaction, Haus der Bayerischen Landwirtschaft
    Herrsching am Ammersee, 14. Oktober.2009
    [URL: http://fsw.informatik.tu-muenchen.de/workshop/workshop2009_program.php]

  • Ejima, S.; Hager, Georg; Fehske, Holger;
    Quantum phase transition in a 1D transport model with boson affected hopping: Luttinger liquid versus charge-density-wave behavior
    In: Physical Review Letters 102 (2009), S. 106404-106407
    [DOI: 10.1103/PhysRevLett.102.106404]

  • Hager, Georg; Stengel, Holger; Zeiser, Thomas; Wellein, Gerhard;
    RZBENCH: performance evaluation of current HPC architechtures using low-level and application benchmarks
    In: Wagner, SiegfriedSteinmetz, MatthiasBode ArndtBrehm Matthias (Hrsg.): High Performance Computing in Science and Engineering, Garching/Munich 2007: Transactions of the Third Joint HLRB and KONWIHR Status and Result Workshop, Dec. 3-4, 2007, Leibniz Supercomputing Centre, Garching/Munich, Germany.
    Berlin, Heidelberg : Springer, 2009, S. 485-501.
    [DOI: 10.1007/978-3-540-69182-2_39]

  • Zeiser, Thomas; Hager, Georg; Wellein, Gerhard; Inayat, Amer; Schwieger, Wilhelm; Heidig, Tobias; Freund, Hannsjörg;
    Selecting an Appropriate Computational Platform for Supporting the Development of New Catalyst Carriers
    In: Innovatives Supercomputing in Deutschland (inSiDE) 7 Spring (2009), S. 12-16
    [URL: http://inside.hlrs.de/htm/Edition_01_09/article_05.html]

  • Habich, Johannes; Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    Speeding up a Lattice Boltzmann Kernel on nVIDIA GPUs
    Vortrag: First International Conference on Parallel, Distributed and Grid Computing for Engineering (PARENG09-S01)
    Pecs, Hungary, 6-8,April.2009

  • Habich, Johannes; Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    Speeding up a Lattice Boltzmann Kernel on nVIDIA GPUs
    In: Topping, B.H.V.; Iványi, P; (Hrsg:) Proceedings of the First International Conference on Parallel, Distributed and Grid Computing for Engineering
    (PARENG2009, Pécs, Hungary, 6-8.April.2009)
    Kippen, Stirlingshire, United Kingdom : Civil-Comp Press, 2009, S. 17. - ISBN 978-1-905088-29-4

  • Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    The world's fastest CPU and SMP node: Some performance results from the NEC SX-9
    In: -; (Hrsg:) Proceedings of the IEEE International Symposium on Parallel&Distributed Processing 2009
    (23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS), Roma, 25-29 Mai)
    IEEE Computer Society : ipdps, 2009, S. 1-8. - ISBN 978-1-4244-3751-1
    [DOI: 10.1109/IPDPS.2009.5161089]

  • Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    The world's fastest CPU and SMP node: Some performance results from the NEC SX-9
    Vortrag: HLRS Results and Review Workshop
    Stuttgart, Oktober.2009

  • Zeiser, Thomas; Hager, Georg; Wellein, Gerhard;
    Vector Computers in a World of Commodity Clusters, Massively Parallel Systems and Many-Core Many-Threaded CPUs: Recent Experience Based on an Advanced Lattice Boltzmann Flow Solver
    In: Nagel, Wolfgang E.Kröner, Dietmar B.Resch, Michael M. (Hrsg.): High Performance Computing in Science and Engineering '08: Transactions of the High Performance Computing Center, Stuttgart (HLRS) 2008.
    Berlin Heidelberg : Springer, 2009, S. 333-347.
    [DOI: 10.1007/978-3-540-88303-6_24]

  • Habich, Johannes; Hager, Georg;
    Windows HPC in Erlangen: Accounting, Monitoring, Projekte
    Vortrag: 2. Treffen der Windows HPC Benutzergruppe in Dresden 2009, Zentrum für Informationsdienste und Hochleistungsrechnen
    Dresden, 30-31.März.2009
    [URL: http://www.rz.rwth-aachen.de/global/show_document.asp?id=aaaaaaaaaabtcij]

2008

2007

2006

2005

2004

2003

  • Wellein, Gerhard; Hager, Georg; Basermann, Achim; Fehske, Holger;
    Fast Sparse Matrix-Vector Multiplication for TeraFlop/s Computers
    In: Palma, José M. L. M.; Dongarra, J.; Hernández, V.; Sousa, A.A.; Waldén, M.; (Hrsg:) High Performance Computing for Computational Science, VECPAR 2002: 5th International Conference, Porto, Portugal, June 26-28, 2002: Selected Papers and Invited Talks
    (VECPAR 2002, Porto, Portugal, June 26-28, 2002)
    Berlin Heidelberg : Springer, 2003, S. 205-207.
    (Lecture Notes in Computer Science) - ISBN 978-3-540-00852-1

  • Fehske, Holger; Wellein, Gerhard; Kampf, Arno P.; Sekania, Michael; Hager, Georg; Weiße, Alexander; Büttner, Helmut; Bishop, Alan R.;
    One-dimensional electron-phonon systems: Mott- versus Peierls-insulators
    In: Wagner, SiegfriedHanke, WernerBode, ArndtDurst (Hrsg.): High Performance Computing in Science and Engineering, Munich 2002: Transactions of the First Joint HLRB and KONWIHR Result and Reviewing Workshop.
    New York, LLC : Springer-Verlag, 2003, S. 339-349.

  • Hager, Georg; Brechtefeld, Frank; Lammers, P.; Wellein, Gerhard;
    Processor Architecture and Application Performance in Modern Supercomputers
    In: inSiDE 1 (2003), S. 8-13
  • Hager, Georg; Deserno, Frank; Wellein, Gerhard;
    Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture
    In: Wagner, SiegfriedHanke, WernerBode, ArndtDurst, Franz (Hrsg.): High Performance Computing in Science and Engineering, Munich 2002: Transactions of the First Joint HLRB and KONWIHR Status and Result Workshop, October 10-11, Technical University of Munich, Germany.
    New York, LLC : Springer-Verlag, 2003, S. 425-442.

2001

Letzte Änderung: 28. April 2014, Historie

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